Paper 2024/1889
IO-Optimized Design-Time Configurable Negacyclic Seven-Step NTT Architecture for FHE Applications
Abstract
FHE enables computations on encrypted data, proving itself to be an essential building block for privacy-preserving applications. However, it involves computationally demanding operations such as polynomial multiplication, with the NTT being the state-of-the-art solution to perform it. Considering that most FHE schemes operate over the negacyclic ring of polynomials, we introduce a novel formulation of the hierarchical Four-Step NTT approach for the negacyclic ring, eliminating the need for pre- and post-processing steps found in the existing methods. To accelerate NTT operations, the FPGA devices offer flexible and powerful computing platforms. We propose an FPGA-based, high-speed, parametric and fully pipelined architecture that implements the improved Seven-Step NTT algorithm, which builds upon the four-step algorithm. Our design supports a wide range of parameters, including ring sizes up to
Metadata
- Available format(s)
-
PDF
- Publication info
- Preprint.
- Keywords
- hardwareFPGAaccelerationhomomorphic encryption
- Contact author(s)
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kocer @ sabanciuniv edu
selim kirbiyik @ sabanciuniv edu
toluntosun @ sabanciuniv edu
ersin alaybeyoglu @ sabanciuniv edu
erkays @ sabanciuniv edu - History
- 2025-05-18: last of 3 revisions
- 2024-11-20: received
- See all versions
- Short URL
- https://ia.cr/2024/1889
- License
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CC BY-NC-ND
BibTeX
@misc{cryptoeprint:2024/1889, author = {Emre Koçer and Selim Kırbıyık and Tolun Tosun and Ersin Alaybeyoğlu and Erkay Savaş}, title = {{IO}-Optimized Design-Time Configurable Negacyclic Seven-Step {NTT} Architecture for {FHE} Applications}, howpublished = {Cryptology {ePrint} Archive, Paper 2024/1889}, year = {2024}, url = {https://eprint.iacr.org/2024/1889} }