A Better Kyber Butterfly for FPGAs

Jonas Bertels; Quinten Norga; Ingrid Verbauwhede

Paper 2024/1367

A Better Kyber Butterfly for FPGAs

Jonas Bertels

, KU Leuven

Quinten Norga

, KU Leuven

Ingrid Verbauwhede

, KU Leuven

Abstract

Kyber was selected by NIST as a Post-Quantum Cryptography Key Encapsulation Mechanism standard. This means that the industry now needs to transition and adopt these new standards. One of the most demanding operations in Kyber is the modular arithmetic, making it a suitable target for optimization. This work offers a novel modular reduction design with the lowest area on Xilinx FPGA platforms. This novel design, through K-reduction and LUT-based reduction, utilizes 49 LUTs and 1 DSP as opposed to Xing and Li’s 2021 CHES design requiring 90 LUTs and 1 DSP for one modular multiplication. Our design is the smallest modular multiplier reported as of today.

Metadata

Available format(s): PDF
Category: Implementation
Publication info: Published elsewhere. FPL 2024
Keywords: CRYSTALS-Kyber Hardware Design FPGA
Contact author(s): jonas bertels @ esat kuleuven be
quinten norga @ esat kuleuven be
ingrid verbauwhede @ esat kuleuven be
History: 2024-09-02: approved; 2024-08-30: received; See all versions
Short URL: https://ia.cr/2024/1367
License: CC BY

BibTeX

@misc{cryptoeprint:2024/1367,
      author = {Jonas Bertels and Quinten Norga and Ingrid Verbauwhede},
      title = {A Better Kyber Butterfly for {FPGAs}},
      howpublished = {Cryptology {ePrint} Archive, Paper 2024/1367},
      year = {2024},
      url = {https://eprint.iacr.org/2024/1367}
}