Paper 2024/1120

A Fast and Efficient SIKE Co-Design: Coarse-Grained Reconfigurable Accelerators with Custom RISC-V Microcontroller on FPGA

Jing Tian, Nanjing University
Bo Wu, Nanjing University
Lang Feng, Nanjing University
Haochen Zhang, Nanjing University
Zhongfeng Wang, Nanjing University
Abstract

This paper proposes a fast and efficient FPGA-based hardware-software co-design for the supersingular isogeny key encapsulation (SIKE) protocol controlled by a custom RISC-V processor. Firstly, we highly optimize the core unit, the polynomial-based field arithmetic logic unit (FALU), with the proposed fast convolution-like multiplier (FCM) to significantly reduce the resource consumption while still maintaining low latency and constant time for all the four SIKE parameters. Secondly, we pack the small isogeny and point operations in hardware, devise a coarse-grained reconfigurable hardware architecture (CGRHA) based on FALU as the co-processor, and apply it to the RISC-V core with customized instructions, effectively avoiding extra time consumption for the data exchange with the software side and meanwhile increasing flexibility. Finally, we code the hardware in SystemVerilog language and the software in C language and run experiments on FPGAs. In the co-processor implementation, the experiment results show that our design for the four SIKE parameters achieves 2.6-4.4x speedup and obtains comparable or better area-time product to or than the state-of-the-art. In the hardware-software co-design experiments, we still have the superiority in speed and only <10\% of extra time is introduced by mutual communication.

Note: This manuscript was submitted to CHES in July 2022 and has been published nowhere else.

Metadata
Available format(s)
PDF
Category
Implementation
Publication info
Preprint.
Keywords
Elliptic curve cryptography (ECC)modular reductionBarrett reductionpolynomial multiplication
Contact author(s)
tianjing @ nju edu cn
wubo @ smail nju edu cn
flang @ nju edu cn
zhanghc0624 @ sina com
zfwang @ nju edu cn
History
2024-07-10: approved
2024-07-09: received
See all versions
Short URL
https://ia.cr/2024/1120
License
Creative Commons Attribution
CC BY

BibTeX

@misc{cryptoeprint:2024/1120,
      author = {Jing Tian and Bo Wu and Lang Feng and Haochen Zhang and Zhongfeng Wang},
      title = {A Fast and Efficient {SIKE} Co-Design: Coarse-Grained Reconfigurable Accelerators with Custom {RISC}-V Microcontroller on {FPGA}},
      howpublished = {Cryptology ePrint Archive, Paper 2024/1120},
      year = {2024},
      note = {\url{https://eprint.iacr.org/2024/1120}},
      url = {https://eprint.iacr.org/2024/1120}
}
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