A Low-Latency High-Order Arithmetic to Boolean Masking Conversion

Jiangxue Liu; Cankun Zhao; Shuohang Peng; Bohan Yang; Hang Zhao; Xiangdong Han; Min Zhu; Shaojun Wei; Leibo Liu

Paper 2024/045

A Low-Latency High-Order Arithmetic to Boolean Masking Conversion

Jiangxue Liu, Beijing National Research Center for Information Science and Technology, School of Integrated Circuits, Tsinghua University, Beijing 100084

Cankun Zhao

, Beijing National Research Center for Information Science and Technology, School of Integrated Circuits, Tsinghua University, Beijing 100084

Shuohang Peng, Beijing National Research Center for Information Science and Technology, School of Integrated Circuits, Tsinghua University, Beijing 100084

Bohan Yang

, Beijing National Research Center for Information Science and Technology, School of Integrated Circuits, Tsinghua University, Beijing 100084

Hang Zhao, Beijing National Research Center for Information Science and Technology, School of Integrated Circuits, Tsinghua University, Beijing 100084

Xiangdong Han, Beijing National Research Center for Information Science and Technology, School of Integrated Circuits, Tsinghua University, Beijing 100084

Min Zhu, Wuxi Micro Innovation Integrated Circuit Design Co., Ltd., Wuxi, China

Shaojun Wei, Beijing National Research Center for Information Science and Technology, School of Integrated Circuits, Tsinghua University, Beijing 100084

Leibo Liu, Beijing National Research Center for Information Science and Technology, School of Integrated Circuits, Tsinghua University, Beijing 100084

Abstract

Masking, an effective countermeasure against side-channel attacks, is commonly applied in modern cryptographic implementations. Considering cryptographic algorithms that utilize both Boolean and arithmetic masking, the conversion algorithm between arithmetic masking and Boolean masking is required. Conventional high-order arithmetic masking to Boolean masking conversion algorithms based on Boolean circuits suffer from performance overhead, especially in terms of hardware implementation. In this work, we analyze high latency for the conversion and propose an improved high-order A2B conversion algorithm. For the conversion of 16-bit variables, the hardware latency can be reduced by 47% in the best scenario. For the case study of second-order 32-bit conversion, the implementation results show that the improved scheme reduces the clock cycle latency by 42% in hardware and achieves a 30% speed performance improvement in software. Theoretically, a security proof of arbitrary order is provided for the proposed high-order A2B conversion. Experimental validations are performed to verify the second-order DPA resistance of second-order implementation. The Test Vector Leakage Assessment does not observe side-channel leakage for hardware and software implementations.

Metadata

Available format(s): PDF
Category: Implementation
Publication info: Preprint.
Keywords: Masking A2B conversion algorithms PINI HPC TVLA
Contact author(s): liujx21 @ mails tsinghua edu cn
zck22 @ mails tsinghua edu cn
psh20 @ mails tsinghua edu cn
bohanyang @ tsinghua edu cn
zhao-h21 @ mails tsinghua edu cn
hanxd2023 @ tsinghua edu cn
zhumin @ mucse com
wsj @ mail tsinghua edu cn
liulb @ tsinghua edu cn
History: 2024-01-12: approved; 2024-01-11: received; See all versions
Short URL: https://ia.cr/2024/045
License: CC BY

BibTeX

@misc{cryptoeprint:2024/045,
      author = {Jiangxue Liu and Cankun Zhao and Shuohang Peng and Bohan Yang and Hang Zhao and Xiangdong Han and Min Zhu and Shaojun Wei and Leibo Liu},
      title = {A Low-Latency High-Order Arithmetic to Boolean Masking Conversion},
      howpublished = {Cryptology ePrint Archive, Paper 2024/045},
      year = {2024},
      note = {\url{https://eprint.iacr.org/2024/045}},
      url = {https://eprint.iacr.org/2024/045}
}