Paper 2023/174
Improved Heuristics for Low-latency Implementations of Linear Layers
Abstract
In many applications, low area and low latency are required for the chip-level implementation of cryptographic primitives. The low-cost implementations of linear layers usually play a crucial role for symmetric ciphers. Some heuristic methods, such as the forward search and the backward search, minimize the number of XOR gates of the linear layer under the minimum latency limitation. For the sake of achieving further optimization for such implementation of the linear layer, we put forward a new general search framework attaching the division optimization and extending base techniques in this paper. In terms of the number of XOR gates and the searching time, our new search algorithm is better than the previous heuristics, including the forward search and the backward search when testing matrices provided by them. We obtain an improved implementation of AES MixColumns requiring only 102 XORs under minimum latency, which outdoes the previous best record provided by the forward search.
Metadata
- Available format(s)
-
PDF
- Publication info
- Published elsewhere. CT-RSA 2023
- Keywords
- Lightweight cryptographyLinear layersLow latencyAES
- Contact author(s)
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qunliu @ mail sdu edu cn
zhaozheng @ mail sdu edu cn
mqwang @ sdu edu cn - History
- 2023-02-15: approved
- 2023-02-12: received
- See all versions
- Short URL
- https://ia.cr/2023/174
- License
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CC BY
BibTeX
@misc{cryptoeprint:2023/174,
author = {Qun Liu and Zheng Zhao and Meiqin Wang},
title = {Improved Heuristics for Low-latency Implementations of Linear Layers},
howpublished = {Cryptology {ePrint} Archive, Paper 2023/174},
year = {2023},
url = {https://eprint.iacr.org/2023/174}
}
