Paper 2022/1071

Performance Evaluation of NIST LWC Finalists on AVR ATmega and ARM Cortex-M3 Microcontrollers

Yuhei Watanabe
Hideki Yamamoto
Hirotaka Yoshida
Abstract

This paper presents results of performance evaluation of NIST Lightweight Cryptography standardization finalists which are implemented by us. Our implementation method puts on the target to reduce RAM consumption on embedded devices. Our target microcontrollers are AVR ATmega 128 and ARM Cortex-M3. We apply our implementation method to five AEAD schemes which include four finalists of the NIST lightweight cryptography standardization and demonstrate the performance evaluation on target microcontrollers. From our performance evaluation of the RAM size, we have achieved 117-byte TinyJAMBU-128 on ATmega 128 and 140-byte TinyJAMBU-128 on ARM Cortex-M3. Our implementation of TinyJAMBU-128 has the smallest RAM of all the target AEAD schemes.

Metadata
Available format(s)
PDF
Category
Implementation
Publication info
Preprint.
Keywords
RAM-optimized implementation NIST LWC Standardization ATmega 128 ARM Cortex-M3
Contact author(s)
yuhei watanabe @ aist go jp
hirotaka yoshida @ aist go jp
History
2022-08-21: approved
2022-08-18: received
See all versions
Short URL
https://ia.cr/2022/1071
License
Creative Commons Attribution
CC BY

BibTeX

@misc{cryptoeprint:2022/1071,
      author = {Yuhei Watanabe and Hideki Yamamoto and Hirotaka Yoshida},
      title = {Performance Evaluation of NIST LWC Finalists on AVR ATmega and ARM Cortex-M3 Microcontrollers},
      howpublished = {Cryptology ePrint Archive, Paper 2022/1071},
      year = {2022},
      note = {\url{https://eprint.iacr.org/2022/1071}},
      url = {https://eprint.iacr.org/2022/1071}
}
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