Cryptology ePrint Archive: Report 2021/464

iTimed: Cache Attacks on the Apple A10 Fusion SoC

Gregor Haas and Seetal Potluri and Aydin Aysu

Abstract: This paper proposes the first cache timing side-channel attacks on one of Apple's mobile devices. Utilizing a recent, permanent exploit named checkm8, we reverse-engineered Apple's BootROM and created a powerful toolkit for running arbitrary hardware security experiments on Apple's in-house designed ARM systems-on-a-chip (SoC). We integrate two additional open-source tools to enhance our own toolkit, further increasing its capability for hardware security research. Using this toolkit, which is a core contribution of our work, we then implement both time-driven and access-driven cache timing attacks as proof-of-concept illustrators. In both cases, we propose statistical innovations which further the state-of-the-art in cache timing attacks. We find that our access-driven attack, at best, can reduce the security of OpenSSL AES-128 to merely 25 bits, while our time-driven attack (with a much weaker adversary) can reduce it to 48 bits. We also quantify that access-driven attacks on the A10 which do not use our statistical improvements are unable to deduce the key, and that our statistical technique reduces the traces needed by the typical time-driven attacks by 21.62 million.

Category / Keywords: implementation / SCA, cache attacks, iPhone

Date: received 9 Apr 2021

Contact author: ghaas at ncsu edu

Available format(s): PDF | BibTeX Citation

Version: 20210412:175435 (All versions of this report)

Short URL: ia.cr/2021/464


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