Cryptology ePrint Archive: Report 2021/1189

A Configurable Crystals-Kyber Hardware Implementation with Side-Channel Protection

Arpan Jati and Naina Gupta and Anupam Chattopadhyay and Somitra Kumar Sanadhya

Abstract: In this work, we present a configurable and side channel resistant implementation of the post-quantum key-exchange algorithm Crystals-Kyber. The implemented design can be configured for different performance and area requirements leading to different trade-offs for different applications. A low area implementation can be achieved in 5269 LUTs and 2422 FFs, whereas a high performance implementation required 7151 LUTs and 3730 FFs. Due to a deeply pipelined architecture, a high operating speed of more than 250 MHz could be achieved on 28nm Xilinx FPGAs. The side channel resistance is implemented using a carefully chosen set of techniques resulting in a low overhead of less than 5%. To the best of our knowledge, this work presents the first side-channel attack protected configurable accelerator for Crystals-Kyber. Furthermore, one of the configuration choices results in the smallest hardware implementation of Crystals-Kyber known in literature.

Category / Keywords: implementation / cryptography,post-quantum,key-exchange,cryptoprocessor,Kyber,fault-resistance,SCA

Date: received 15 Sep 2021

Contact author: naina003 at e ntu edu sg, arpanj at iiitd ac in

Available format(s): PDF | BibTeX Citation

Version: 20210917:090757 (All versions of this report)

Short URL: ia.cr/2021/1189


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