Cryptology ePrint Archive: Report 2020/897

Folding BIKE: Scalable Hardware Implementation for Reconfigurable Devices

Jan Richter-Brockmann and Johannes Mono and Tim GŁneysu

Abstract: Contemporary digital infrastructures and systems use and trust PKC to exchange keys over insecure communication channels. With the development and progress in the research field of quantum computers, well established schemes like RSA and ECC are more and more threatened. The urgent demand to find and standardize new schemes - which are secure in a post-quantum world - was also realized by the NIST which announced a PQC Standardization Project in 2017. Recently, the round three candidates were announced and one of the alternate candidates is the KEM scheme BIKE.

In this work, we investigate different strategies to efficiently implement the BIKE algorithm on FPGA. To this extend, we improve already existing polynomial multipliers, propose efficient strategies to realize polynomial inversions, and implement the BGF decoder for the first time. Additionally, our implementation is designed to be scalable and generic with the BIKE specific parameters. All together, the fastest designs achieve latencies of 2.69 ms for the key generation, 0.1 ms for the encapsulation, and 1.89 ms for the decapsulation considering the lowest security level.

Category / Keywords: implementation / BIKE, QC-MDPC, PQC, Reconfigurable Devices, FPGA

Original Publication (in the same form): IEEE Transactions on Computers
DOI:
10.1109/TC.2021.3078294

Date: received 16 Jul 2020, last revised 17 May 2021

Contact author: jan richter-brockmann at rub de

Available format(s): PDF | BibTeX Citation

Note: The update version matches the accepted paper in the IEEE Transactions on Computers.

Version: 20210517:083122 (All versions of this report)

Short URL: ia.cr/2020/897


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