Cryptology ePrint Archive: Report 2020/1221

Verifiable Functional Encryption using Intel SGX

Tatsuya Suzuki and Keita Emura and Toshihiro Ohigashi and Kazumasa Omote

Abstract: Most functional encryption schemes implicitly assume that inputs to decryption algorithms, i.e., secret keys and ciphertexts, are generated honestly. However, they may be tampered by malicious adversaries. Thus, verifiable functional encryption (VFE) was proposed by Badrinarayanan et al. in ASIACRYPT 2016 where anyone can publicly check the validity of secret keys and ciphertexts. They employed indistinguishability-based (IND-based) security due to an impossibility result of simulation-based (SIM-based) VFE even though SIM-based security is more desirable. In this paper, we propose a SIM-based VFE scheme. To bypass the impossibility result, we introduce a trusted setup assumption. Although it appears to be a strong assumption, we demonstrate that it is reasonable in a hardware-based construction, e.g., Fisch et al. in ACM CCS 2017. Our construction is based on a verifiable public-key encryption scheme (Nieto et al. in SCN 2012), a signature scheme, and a secure hardware scheme, which we refer to as VFE-HW. Finally, we discuss an our implementation of VFE-HW using Intel Software Guard Extensions (Intel SGX).

Category / Keywords: public-key cryptography / Functional Encryption, Intel SGX, Verifiability, Simulation Security

Date: received 4 Oct 2020

Contact author: s2030117 at s tsukuba ac jp

Available format(s): PDF | BibTeX Citation

Version: 20201006:095115 (All versions of this report)

Short URL: ia.cr/2020/1221


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