Paper 2019/721

Optimized SIKE Round 2 on 64-bit ARM

Hwajeong Seo, Amir Jalali, and Reza Azarderakhsh


In this work, we present the rst highly-optimized implementation of Supersingular Isogeny Key Encapsulation (SIKE) submitted to NIST's second round of post quantum standardization process, on 64-bit ARMv8 processors. To the best of our knowledge, this work is the rst optimized implementation of SIKE round 2 on 64-bit ARM over SIKEp434 and SIKEp610. The proposed library is explicitly optimized for these two security levels and provides constant-time implementation of the SIKE mechanism on ARMv8-powered embedded devices. We adapt dierent optimization techniques to reduce the total number of underlying arithmetic operations on the led level. In particular, the benchmark results on embedded processors equipped with ARM Cortex- A53@1.536GHz show that the entire SIKE round 2 key encapsulation mechanism takes only 84 ms at NIST's security level 1. Considering SIKE's extremely small key size in comparison to other candidates, our result implies that SIKE is one of the promising candidates for key encapsulation mechanism on embedded devices in the quantum era.

Available format(s)
Publication info
Preprint. MINOR revision.
Post-quantum cryptographyisogeny-based cryptography64-bit ARM processorARM assemblykey encapsulation mechanism
Contact author(s)
hwajeong84 @ gmail com
azarderakhsh @ gmail com
amirjalali65 @ gmail com
2019-06-18: received
Short URL
Creative Commons Attribution


      author = {Hwajeong Seo and Amir Jalali and Reza Azarderakhsh},
      title = {Optimized SIKE Round 2 on 64-bit ARM},
      howpublished = {Cryptology ePrint Archive, Paper 2019/721},
      year = {2019},
      note = {\url{}},
      url = {}
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