Cryptology ePrint Archive: Report 2019/322

A High-Speed Constant-Time Hardware Implementation of NTRUEncrypt SVES

Farnoud Farahmand and Malik Umar Sharif and Kevin Briggs and Kris Gaj

Abstract: In this paper, we present a high-speed constant time hardware implementation of NTRUEncrypt Short Vector Encryption Scheme (SVES), fully compliant with the IEEE 1363.1 Standard Specification for Public Key Cryptographic Techniques Based on Hard Problems over Lattices. Our implementation follows an earlier proposed Post-Quantum Cryptography (PQC) Hardware Application Programming Interface (API), which facilitates its fair comparison with implementations of other PQC schemes. The paper contains the detailed flow and block diagrams, timing analysis, as well as results in terms of latency (in clock cycles), maximum clock frequency, and resource utilization in modern high-performance Field Programmable Gate Arrays (FPGAs). Our design takes full advantage of the ability to parallelize the major operation of NTRU, polynomial multiplication, in hardware. As a result, the execution time bottleneck shifts to the hash function, SHA-256, which is sequential in nature and as a result cannot be easily sped up in hardware. The obtained FPGA results for NTRU Encrypt SVES are compared with the equivalent results for Classic McEliece, a competing, well-established Post-Quantum Cryptography encryption scheme, with a long history of unsuccessful attempts at breaking. Our code for NTRUEncrypt SVES is being made open-source to speed-up further design-space exploration and benchmarking on multiple hardware platforms.

Category / Keywords: implementation / NTRU, lattice-based, hardware, API, P1363.1

Original Publication (with minor differences): 2018 International Conference on Field Programmable Technology (ICFPT)

Date: received 23 Mar 2019

Contact author: ffarahma at gmu edu

Available format(s): PDF | BibTeX Citation

Version: 20190329:130653 (All versions of this report)

Short URL: ia.cr/2019/322


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