Cryptology ePrint Archive: Report 2018/341

Comparison of Cost of Protection Against Differential Power Analysis of Selected Authenticated Ciphers

William Diehl and Abubakr Abdulgadir and Farnoud Farahmand and Jens-Peter Kaps and Kris Gaj

Abstract: Authenticated ciphers, like all physical implementations of cryptography, are vulnerable to side-channel attacks, including differential power analysis (DPA). The t-test leakage detection methodology has been used to verify improved resistance of block ciphers to DPA after application of countermeasures. However, extension of the t-test methodology to authenticated ciphers is non-trivial, since authenticated ciphers require additional input and output conditions, complex interfaces, and long test vectors interlaced with protocol necessary to describe authenticated cipher operations. In this research we augment an existing side-channel analysis architecture (FOBOS) with t-test leakage detection for authenticated ciphers. We use this capability to show that implementations in the Spartan-6 FPGA of the CAESAR Round 3 candidates ACORN, ASCON, CLOC (AES and TWINE), SILC (AES, PRESENT, and LED), JAMBU (AES and SIMON), and Ketje Jr., as well as AES-GCM, are vulnerable to 1st order DPA. We then implement versions of the above ciphers, protected against 1st order DPA, using threshold implementations. The t-test leakage detection methodology is used to verify improved resistance to 1st order DPA of the protected cipher implementations. Finally, we benchmark unprotected and protected cipher implementations in the Spartan-6 FPGA, and compare the costs of 1st order DPA protection in terms of area, frequency, throughput, throughput-to-area (TP/A) ratio, power, and energy-per-bit. Our results show that ACORN has the lowest area (in LUTs), the highest TP/A ratio, and is the most energy-efficient of all DPA-resistant implementations. However, Ketje Jr. has the highest throughput.

Category / Keywords: implementation / Cryptography, authenticated cipher, field programmable gate array, power analysis, side channel attack, countermeasure, lightweight, t-test

Original Publication (with major differences): IEEE International Symposium on Hardware Oriented Security and Trust (HOST 2018)

Date: received 11 Apr 2018

Contact author: wdiehl at gmu edu

Available format(s): PDF | BibTeX Citation

Version: 20180416:211106 (All versions of this report)

Short URL: ia.cr/2018/341


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