Cryptology ePrint Archive: Report 2017/674

Transparent Memory Encryption and Authentication

Mario Werner and Thomas Unterluggauer and Robert Schilling and David Schaffenrath and Stefan Mangard

Abstract: Security features of modern (SoC) FPAGs permit to protect the confidentiality of hard- and software IP when the devices are powered off as well as to validate the authenticity of IP when being loaded at startup. However, these approaches are insufficient since attackers with physical access can also perform attacks during runtime, demanding for additional security measures. In particular, RAM used by modern (SoC) FPGAs is under threat since RAM stores software IP as well as all kinds of other sensitive information during runtime.

To solve this issue, we present an open-source framework for building transparent RAM encryption and authentication pipelines, suitable for both FPGAs and ASICs. The framework supports various ciphers and modes of operation as shown by our comprehensive evaluation on a Xilinx Zynq-7020 SoC. For encryption, the ciphers Prince and AES are used in the ECB, CBC and XTS mode. Additionally, the authenticated encryption cipher Ascon is used both standalone and within a TEC tree. Our results show that the data processing of our encryption pipeline is highly efficient with up to 94% utilization of the read bandwidth that is provided by the FPGA interface. Moreover, the use of a cryptographically strong primitive like Ascon yields highly practical results with 54% bandwidth utilization.

Category / Keywords: implementation / RAM,encryption,authentication,Zynq,FPGA

Original Publication (in the same form): FPL2017

Date: received 6 Jul 2017, last revised 24 Aug 2017

Contact author: mario werner at iaik tugraz at

Available format(s): PDF | BibTeX Citation

Version: 20170824:140022 (All versions of this report)

Short URL: ia.cr/2017/674

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