Paper 2015/786

Buying AES Design Resistance with Speed and Energy

Jean-Michel Cioranesco, Roman Korkikian, David Naccache, and Rodrigo Portella do Canto

Abstract

Fault and power attacks are two common ways of extracting secrets from tamper-resistant chips. Although several protections have been proposed to thwart these attacks, resistant designs usually claim significant area or speed overheads. Furthermore, circuit-level countermeasures are usually not reconfigurable at runtime. This paper exploits the AES’ algorithmic features to propose low-cost and low-latency protections. We provide Verilog and FPGA implementation details. Using our design, real-life applications can be configured during runtime to meet the user’s needs and the system’s constraints.

Metadata
Available format(s)
PDF
Category
Implementation
Publication info
Preprint. MINOR revision.
Keywords
side channel attacksfault attacksAES
Contact author(s)
david naccache @ ens fr
History
2015-08-10: revised
2015-08-07: received
See all versions
Short URL
https://ia.cr/2015/786
License
Creative Commons Attribution
CC BY

BibTeX

@misc{cryptoeprint:2015/786,
      author = {Jean-Michel Cioranesco and Roman Korkikian and David Naccache and Rodrigo Portella do Canto},
      title = {Buying AES Design Resistance with Speed and Energy},
      howpublished = {Cryptology ePrint Archive, Paper 2015/786},
      year = {2015},
      note = {\url{https://eprint.iacr.org/2015/786}},
      url = {https://eprint.iacr.org/2015/786}
}
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