Paper 2026/556

TP-NTT: Batch NTT Hardware with Application to Relinearization

Emre Koçer, Sabanci University
Tolun Tosun, Sabanci University
Beren Aydoğan, Sabanci University
Erkay Savaş, Sabanci University
Furkan Turan, KU Leuven
Ingrid Verbauwhede, KU Leuven
Abstract

Fully Homomorphic Encryption (FHE) enables arbitrary computation on encrypted data without decryption, providing strong privacy guarantees for secure cloud computing, encrypted analytics, and privacy-preserving machine learning. However, practical deployment of FHE remains limited by the high computational cost of polynomial arithmetic over large modular rings. In particular, Number Theoretic Transform (NTT)–based polynomial multiplication dominates the execution time of modern lattice-based FHE schemes. In this work, we present TP-NTT, a scalable, throughput-optimized NTT architecture supporting a wide range of ring dimensions used in FHE, from $2^{10}$ to $2^{16}$. Our design applies optimizations at multiple levels, from modular arithmetic to the NTT algorithm itself, including multi-dimensional decomposition without requiring additional multiplication blocks. The decomposition dimensionality is configurable at design time, supporting 2-D, 3-D, and 4-D decompositions, each advantageous in specific scenarios. Furthermore, TP-NTT provides design-time configurable throughput. Combined with its scalable architecture, this enables significant advantages for batch NTT operations compared to other works in the literature. At $n=2^{16}$, it outperforms the best-performing prior design by $1.33\times$ in average latency while achieving $1.26\times$ better area–time-product (ATP). To demonstrate its efficiency, we present a case-study on FHE relinearization, focusing on the BFV scheme. We propose a relinearization accelerator that leverages the fast batch NTT capability of TP-NTT, achieving $67.21\times$ speed-up over state-of-the-art software implementations and highlighting TP-NTT’s effectiveness in real-world FHE applications.

Metadata
Available format(s)
PDF
Category
Implementation
Publication info
Preprint.
Keywords
FHE Hardware Acceleration FPGA
Contact author(s)
kocer @ sabanciuniv edu
toluntosun @ sabanciuniv edu
beren aydogan @ sabanciuniv edu
erkays @ sabanciuniv edu
furkan turan @ esat kuleuven be
ingrid verbauwhede @ esat kuleuven be
History
2026-06-16: last of 2 revisions
2026-03-20: received
See all versions
Short URL
https://ia.cr/2026/556
License
Creative Commons Attribution
CC BY

BibTeX

@misc{cryptoeprint:2026/556,
      author = {Emre Koçer and Tolun Tosun and Beren Aydoğan and Erkay Savaş and Furkan Turan and Ingrid Verbauwhede},
      title = {{TP}-{NTT}: Batch {NTT} Hardware with Application to Relinearization},
      howpublished = {Cryptology {ePrint} Archive, Paper 2026/556},
      year = {2026},
      url = {https://eprint.iacr.org/2026/556}
}
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