A Hardware/Software Co-Optimization of HQC Using Tightly-Coupled Accelerators on a 32-bit Ibex Core

Seog Chung Seo; YoungBeom Kim

Paper 2026/478

A Hardware/Software Co-Optimization of HQC Using Tightly-Coupled Accelerators on a 32-bit Ibex Core

Seog Chung Seo

, Kookmin University

YoungBeom Kim

, Kookmin University

Abstract

We present Hardware/Software co-optimization of Hamming Quasi-Cyclic (HQC) enabled by tightly coupled accelerators implemented on a 32-bit Ibex RISC-V core. On the hardware side, we propose a unified multiplier capable of efficiently performing carryless multiplication for both polynomial multiplication over F_2[X]/(X^{n}−1) and multiplication over F_2^{8}. We also design a Keccak permutation accelerator to support efficient randomness sampling. On the software side, we identify the optimal combination of Toom–Cook and Karatsuba methods for efficient polynomial multiplication on the Ibex core and enhance its performance by minimizing the number of memory accesses during its execution.With our co-optimization strategies, our HQC implementation achieves a performance improvement of several tens of times over the reference implementation.

Metadata

Available format(s): PDF
Category: Implementation
Publication info: Published elsewhere. Minor revision. IEEE Transactions on Circuits and Systems II: Express Briefs
DOI: 10.1109/TCSII.2026.3668482
Keywords: PQC HQC RISC-V Ibex-core Accelerator ISE
Contact author(s): scseo @ kookmin ac kr
darania @ kookmin ac kr
History: 2026-03-09: revised; 2026-03-08: received; See all versions
Short URL: https://ia.cr/2026/478
License: CC BY

BibTeX

@misc{cryptoeprint:2026/478,
      author = {Seog Chung Seo and YoungBeom Kim},
      title = {A Hardware/Software Co-Optimization of {HQC} Using Tightly-Coupled Accelerators on a 32-bit Ibex Core},
      howpublished = {Cryptology {ePrint} Archive, Paper 2026/478},
      year = {2026},
      doi = {10.1109/TCSII.2026.3668482},
      url = {https://eprint.iacr.org/2026/478}
}