Paper 2026/2726
Efficient Polynomial Multiplier Architectures for ML-KEM on Resource-Constrained FPGAs
Abstract
The Number Theoretic Transform (NTT) is a key component of polynomial multiplication in Kyber, making its efficient hardware implementation essential for post-quantum cryptographic applications. This paper presents two hardware architectures for Kyber polynomial arithmetic, supporting the NTT, inverse NTT (INTT) and point-wise multiplication (PWM) operations. The first architecture employs a single processing element (PE) to reduce hardware area, while the second uses two PEs to achieve higher throughput and efficiency. Both architectures incorporate a low-complexity modular multiplication and reduction method tailored to the Kyber modulus q = 3329, a unified butterfly unit supporting NTT, INTT, and PWM, and constant-geometry data access with dedicated address-generation algorithms. The dual-PE architecture is implemented without dedicated DSP blocks or BRAMs. FPGA implementation results demonstrate that the dual-PE architecture achieves the lowest area-time product and highest frequency among the evaluated state-of-the-art designs, while providing an effective trade-off between hardware area and execution time.
Metadata
- Available format(s)
-
PDF
- Category
- Implementation
- Publication info
- Preprint.
- Keywords
- KyberML-KEMNumber-theoretic transformPolynomial multiplicationPost-quantum cryptographyFPGA
- Contact author(s)
-
h_naderivarandi @ sbu ac ir
r_salarifard @ sbu ac ir - History
- 2026-11-05: approved
- 2026-11-02: received
- See all versions
- Short URL
- https://ia.cr/2026/2726
- License
-
CC BY-NC-ND
BibTeX
@misc{cryptoeprint:2026/2726,
author = {Hossein Naderi Varandi and Raziye Salarifard},
title = {Efficient Polynomial Multiplier Architectures for {ML}-{KEM} on Resource-Constrained {FPGAs}},
howpublished = {Cryptology {ePrint} Archive, Paper 2026/2726},
year = {2026},
url = {https://eprint.iacr.org/2026/2726}
}
