Paper 2026/2505
AVX-512 Acceleration of SQIsign 3.0 Verification
Abstract
SQIsign is a compact isogeny-based signature scheme. We present a low-latency AVX-512 implementation of complete SQIsign 3.0 verification at security levels I, III, and V. Our implementation provides vectorized curve-side verification, including the Superglue transition, and introduces dynamic-programming strategies for the degree-$2^\ell$ and theta-model $(2,2)$-isogeny chains. The strategies account for batched point evaluation and the preparation of SIMD data. On an Intel Core i7-11800H running native Ubuntu 24.04, the complete verifiers achieve $2.14\times$, $2.08\times$, and $2.34\times$ speedups, respectively, over the SQIsign 3.0 Broadwell reference verifiers (the optimized 64-bit assembly implementation).
Note: We added the implementation details of SQIsign 3.0 key generation and signing (in Appendix A).
Metadata
- Available format(s)
-
PDF
- Category
- Implementation
- Publication info
- Preprint.
- Keywords
- SQIsignAVX-512dynamic programmingisogeny chains
- Contact author(s)
-
huzhi_math @ csu edu cn
zhaochan3 @ mail sysu edu cn - History
- 2026-10-17: approved
- 2026-10-16: received
- See all versions
- Short URL
- https://ia.cr/2026/2505
- License
-
CC BY-NC-ND
BibTeX
@misc{cryptoeprint:2026/2505,
author = {Yunqi Wen and Xuzhe Liu and Zhi Hu and Saiyu Wang and Chang-An Zhao},
title = {{AVX}-512 Acceleration of {SQIsign} 3.0 Verification},
howpublished = {Cryptology {ePrint} Archive, Paper 2026/2505},
year = {2026},
url = {https://eprint.iacr.org/2026/2505}
}
