Staggered Instruction-Fetch Duplication: A Lightweight Processor-Level Countermeasure Against Fault Injection

Shoei Nashimoto; Naoya Okada; Yuichiro Murachi

Paper 2026/2440

Staggered Instruction-Fetch Duplication: A Lightweight Processor-Level Countermeasure Against Fault Injection

Shoei Nashimoto

, Mitsubishi Electric (Japan)

Naoya Okada, Mitsubishi Electric (Japan)

Yuichiro Murachi, Mitsubishi Electric (Japan)

Abstract

Fault attacks exploit transient hardware faults to bypass software-level security checks in embedded processors. Processor-level redundancy can detect such faults, but duplicating the whole processor is costly for resource-constrained devices. This paper proposes Staggered Instruction-Fetch Duplication (SIFD), a lightweight processor-level countermeasure based on instruction-fetch redundancy. SIFD fetches each instruction twice in consecutive cycles, while fetching two different instructions in every fetch cycle. This staggered schedule detects inconsistent fetch results without full processor duplication, compiler support, or cryptographic hardware. We implement SIFD on a custom RV32I processor and evaluate it on an Artix-7 FPGA using clock fault injection (CFI) and electromagnetic fault injection (EMFI). SIFD increases slice utilization by 15.0% and execution time by 16.3%. It reduces the attack success rate from 0.86% to below 0.01% under CFI and from 0.32% to 0.13% under EMFI. It also detects 73.18% of CFI attempts and 11.44% of EMFI attempts. These results indicate that SIFD can convert many fault effects into explicit detections and reduce successful fault-injection outcomes, especially under CFI.

Note: The author list differs from the published version owing to an error made during submission; see the footnote on the first page.

Metadata

Available format(s): PDF
Category: Implementation
Publication info: Published elsewhere. Minor revision. ASP-DAC
DOI: 10.1145/3840404.3848186
Keywords: Fault injection attack Countermeasure RISC-V Processor
Contact author(s): Nashimoto Shoei @ bx mitsubishielectric co jp
History: 2026-10-14: approved; 2026-10-10: received; See all versions
Short URL: https://ia.cr/2026/2440
License: CC BY

BibTeX

@misc{cryptoeprint:2026/2440,
      author = {Shoei Nashimoto and Naoya Okada and Yuichiro Murachi},
      title = {Staggered Instruction-Fetch Duplication: A Lightweight Processor-Level Countermeasure Against Fault Injection},
      howpublished = {Cryptology {ePrint} Archive, Paper 2026/2440},
      year = {2026},
      doi = {10.1145/3840404.3848186},
      url = {https://eprint.iacr.org/2026/2440}
}