Paper 2026/2169

Hardware-Adapted SIMD Optimization of AIMer v3 on x86 and Cortex-M55

Abstract

AIMer v3 replaces AIM2 with AIM3. We test whether SIMD methods developed for AIM2 can accelerate AIM3 while preserving its results. We port the field-arithmetic, affine, party-parallel, and SHAKE methods of the earlier AVX-512 implementation to AIMer v3 and implement the same operations for AVX2. For Cortex-M55 MVE, we use 16-bit polynomial partial products for field multiplication, group corresponding 32-bit words from four parties, and vectorize both affine layers, including the input layer introduced in AIM3. The implementations preserve AIMer v3’s mathematical structure and proof procedures. For all six parameter sets, their outputs match the official known-answer tests and the reference results in differential tests. Relative to the reference on each platform, AVX2 and AVX-512 accelerate signing and verification by 3.14–4.41× and 4.59–6.55×, respectively. Cortex-M55 MVE accelerates the same operations by 1.28–1.91×.