Paper 2026/1615
KORD: Breaking the Key-Generation Bottleneck in Dealerless Function Secret Sharing via Protocol–Hardware Co-Design
, College of Computer Science and Technology, National University of Defense Technology, Changsha, China, Key Laboratory of Advanced Microprocessor Chips and Systems, National University of Defense Technology, Changsha, China, College of Computer Science and Technology, National University of Defense Technology, Changsha, China, College of Computer Science and Technology, National University of Defense Technology, Changsha, China, College of Computer Science and Technology, National University of Defense Technology, Changsha, China, College of Computer Science and Technology, National University of Defense Technology, Changsha, ChinaAbstract
Function secret sharing (FSS) has become a core primitive in privacy‑preserving computation. However, each FSS invocation requires a fresh pair of function keys, typically produced by a trusted dealer—a dependency that expands the system's trust boundary and hinders practical deployment. Existing dealerless protocols eliminate this dependency, but incur substantial communication and a number of interaction rounds that grows linearly with the input bit‑width, making key generation a major bottleneck. This paper presents KORD, a protocol–hardware co‑design that dramatically reduces the cost of dealerless FSS key generation. At its core is a pair of chips that establish a common root of trust through mutual attestation and, within it, reconstruct FSS keys—eliminating the need for a dealer. This root of trust further forms a security boundary within which KORD restructures the generation protocol, collapsing the interaction of prior dealerless protocols into a single round, independent of GGM depth. A cross‑key scheduling scheme then interleaves independent GGM‑tree traversals, sustaining high computational throughput. KORD reduces key‑generation communication per operation by $7{,}633$–$70{,}274\times$ over the state‑of‑the‑art distributed FSS protocol. On a ZCU102 FPGA, cross‑key interleaving lifts AES lane utilization from $8.3\%$ to a board‑measured $99.0\%$, for $11.60$ million $32$-bit DPF keys per second at $187.5\,\text{MHz}$ on a $21.5\,\text{K}$ LUT engine ($12.38\,\text{M}$ at the separately validated $200\,\text{MHz}$ operating point). On private ResNet‑18 inference, key generation's share of end‑to‑end time falls to $10.1\%$, from $82.6\%$ under a trusted dealer and over $96\%$ under the dealerless baseline.
Note: This preprint is submitted to HPCA 2027. This work presents KORD, a protocol‑hardware co‑design for accelerating dealer‑less function‑secret‑sharing key‑generation with FPGA hardware engine.
Metadata
- Available format(s)
-
PDF
- Category
- Cryptographic protocols
- Publication info
- Preprint.
- Keywords
- Function Secret SharingDealer‑lessProtocol‑Hardware Co‑designSecure Multi‑party Computation
- Contact author(s)
-
pengyijing @ nudt edu cn
liulin16 @ nudt edu cn
xyj1997 @ nudt edu cn
fushaojing @ nudt edu cn
lishaoqing @ nudt edu cn
wangyaohua @ nudt edu cn
chromao @ nudt edu cn
gaoyang @ nudt edu cn - History
- 2026-08-06: approved
- 2026-08-05: received
- See all versions
- Short URL
- https://ia.cr/2026/1615
- License
-
CC BY-NC-ND
BibTeX
@misc{cryptoeprint:2026/1615,
author = {Yijing Peng and Lin Liu and Yujie Xue and Shaojing Fu and Shaoqing Li and Yaohua Wang and Rongmao Chen and Yang Guo},
title = {{KORD}: Breaking the Key-Generation Bottleneck in Dealerless Function Secret Sharing via Protocol–Hardware Co-Design},
howpublished = {Cryptology {ePrint} Archive, Paper 2026/1615},
year = {2026},
url = {https://eprint.iacr.org/2026/1615}
}
