Optimization of Hardware Architecture for Quantum Key Distribution

Raja Adhithan Radhakrishnan

Paper 2026/1359

Optimization of Hardware Architecture for Quantum Key Distribution

Raja Adhithan Radhakrishnan

Abstract

The main objective of this paper is to acceler ate the post-processing of Quantum Key Distribution (QKD) using an energy-efficient pipelined architecture implemented on a Field-Programmable Gate Array (FPGA). The proposed architecture aims to improve processing speed while efficiently utilizing hardware resources. In addition, this work compares the proposed approach with existing approaches to demonstrate its performance and resource efficiency.

Metadata

Available format(s): PDF
Category: Implementation
Publication info: Preprint.
Keywords: FPGA Post processing of QKD Pipelined Architecture Energy efficiency
Contact author(s): r rajaadhithan @ gmail com
History: 2026-07-06: approved; 2026-07-02: received; See all versions
Short URL: https://ia.cr/2026/1359
License: CC BY

BibTeX

@misc{cryptoeprint:2026/1359,
      author = {Raja Adhithan Radhakrishnan},
      title = {Optimization of Hardware Architecture for Quantum Key Distribution},
      howpublished = {Cryptology {ePrint} Archive, Paper 2026/1359},
      year = {2026},
      url = {https://eprint.iacr.org/2026/1359}
}