Paper 2026/1306

TETRIS: Automated Design Space Exploration of Randomness–Latency Trade-offs in Masked Hardware

Abstract

Given a fixed security order, the randomness and latency of masked hardware present a trade-off. This trade-off has not been structurally examined well enough to enable an efficient search for a user-optimal (randomness/latency efficient) masked design. Gadget-based masking has simplified masking using masked functions called \textit{gadgets} corresponding to simpler (unmasked) functions as building blocks for larger masked designs. These gadgets, in turn, have masking-order dependent latency-randomness costs, lending a structure to the randomness and latency of gadget-based masked hardware. This structure enables automated Design-Space Exploration (DSE) of gadget-based masked hardware that takes in a user's constraints on randomness (or latency) to arrive at the latency (randomness)- optimal assignment of gadgets with less area and vice versa. This article introduces a software-level DSE approach the basis of which are the two DSE algorithms - Minimize Latency under Randomness Constraints (MLRC) and Minimize Randomness under Latency Constraints (MRLC) which are duals of each other. While prior work solves the problem of optimizing masked hardware by formulating a global SAT optimization, our results show that gadget-based masked hardware using Probe-Isolating Non-Interference (PINI) gadgets embody a structured trade-off lending efficient heuristic-based solutions instead of relying on heavy global optimizations. This gives our tool comparable to superior area results in under a millisecond - a speedup of several orders of magnitude - to the SOTA.

Note: A revised version will be posted in due course.