Chiplet-Based Techniques for Scalable and Memory-Aware Multi-Scalar Multiplication

Florian Hirner; Florian Krieger; Sujoy Sinha Roy

Paper 2025/252

Chiplet-Based Techniques for Scalable and Memory-Aware Multi-Scalar Multiplication

Florian Hirner

, Graz University of Technology

Florian Krieger

, Graz University of Technology

Sujoy Sinha Roy, Graz University of Technology

Abstract

This paper presents a high-performance architecture for accelerating Multi-Scalar Multiplication (MSM) on ASIC platforms, targeting cryptographic applications with high throughput demands. Unlike prior MSM accelerators that focus solely on efficient processing elements (PEs), our chiplet-based design optimally balances area, power, and computational throughput. We identify a mixed window configuration of 12- and 13-bit windows that enables an efficient multi-PE integration of 10 PEs per chiplet. Our single-PE design achieves a 1.37x speedup and 1.3x area reduction over prior works, while the multi-PE chiplet design improves the area-time product by 2.2x, offering scalability, lower production costs, and higher manufacturing yields.

Metadata

Available format(s): PDF
Category: Implementation
Publication info: Preprint.
Keywords: Multiplication Zero-knowledge proofs Hardware Acceleration Scalable Chiplet Architecture Parallel Computing
Contact author(s): florian hirner @ tugraz at
florian krieger @ tugraz at
sujoy sinharoy @ tugraz at
History: 2025-02-18: approved; 2025-02-17: received; See all versions
Short URL: https://ia.cr/2025/252
License: CC BY

BibTeX

@misc{cryptoeprint:2025/252,
      author = {Florian Hirner and Florian Krieger and Sujoy Sinha Roy},
      title = {Chiplet-Based Techniques for Scalable and Memory-Aware Multi-Scalar Multiplication},
      howpublished = {Cryptology {ePrint} Archive, Paper 2025/252},
      year = {2025},
      url = {https://eprint.iacr.org/2025/252}
}