Paper 2025/137
FINAL bootstrap acceleration on FPGA using DSP-free constant-multiplier NTTs
Abstract
This work showcases Quatorze-bis, a state-of-the-art Number Theoretic Transform circuit for TFHE-like cryptosystems on FPGAs. It contains a novel modular multiplication design for modular multiplication with a constant for a constant modulus. This modular multiplication design does not require any DSP units or any dedicated multiplier unit, nor does it require extra logic when compared to the state-of-the-art modular multipliers. Furthermore, we present an implementation of a constant multiplier Number Theoretic Transform design for TFHE-like schemes. Lastly, we use this Number Theoretic Transform design to implement a FINAL hardware accelerator for the AMD Alveo U55c which improves the Throughput metric of TFHE-like cryptosystems on FPGAs by a factor 9.28x over Li et al.'s NFP CHES 2024 accelerator and by 10-25% over the absolute state-of-the-art design FPT while using one third of FPTs DSPs.
Note: (The name Quatorze-bis is a reference to the speed of the design. Airplane speed in meters/hour = bootstrapping speed in bootstraps/second)
Metadata
- Available format(s)
-
PDF
- Category
- Implementation
- Publication info
- Preprint.
- Keywords
- NTTFHEHardware DesignFPGATFHE
- Contact author(s)
-
jonas bertels @ esat kuleuven be
hilder @ unicamp br
ingrid verbauwhede @ esat kuleuven be - History
- 2025-01-29: revised
- 2025-01-28: received
- See all versions
- Short URL
- https://ia.cr/2025/137
- License
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CC BY
BibTeX
@misc{cryptoeprint:2025/137, author = {Jonas Bertels and Hilder V. L. Pereira and Ingrid Verbauwhede}, title = {{FINAL} bootstrap acceleration on {FPGA} using {DSP}-free constant-multiplier {NTTs}}, howpublished = {Cryptology {ePrint} Archive, Paper 2025/137}, year = {2025}, url = {https://eprint.iacr.org/2025/137} }