Paper 2024/367
Accelerating SLH-DSA by Two Orders of Magnitude with a Single Hash Unit
Abstract
We report on efficient and secure hardware implementation techniques for the FIPS 205 SLH-DSA Hash-Based Signature Standard. We demonstrate that very significant overall performance gains can be obtained from hardware that optimizes the padding formats and iterative hashing processes specific to SLH-DSA. A prototype implementation, SLotH, contains Keccak/SHAKE, SHA2-256, and SHA2-512 cores and supports all 12 parameter sets of SLH-DSA. SLotH also supports side-channel secure PRF computation and Winternitz chains. SLotH drivers run on a small RISC-V control core, as is common in current Root-of-Trust (RoT) systems.
The new features make SLH-DSA on SLotH many times faster compared to similarly-sized general-purpose hash accelerators. Compared to unaccelerated microcontroller implementations, the performance of SLotH's SHAKE variants is up to
Note: (Preliminary version of this paper appeared in the Fifth NIST PQC Standardization Conference, April 10-12, 2024, Rockville, Maryland.) The related software and hardware source code is available at: https://github.com/slh-dsa/sloth CRYPTO 2024 artifact: https://artifacts.iacr.org/crypto/2024/a7/
Metadata
- Available format(s)
-
PDF
- Category
- Implementation
- Publication info
- A minor revision of an IACR publication in CRYPTO 2024
- DOI
- 10.1007/978-3-031-68376-3_9
- Keywords
- FIPS 205SLH-DSASPHINCS+Root-of-TrustSide-Channel Security
- Contact author(s)
- markku-juhani saarinen @ tuni fi
- History
- 2024-12-06: last of 5 revisions
- 2024-02-28: received
- See all versions
- Short URL
- https://ia.cr/2024/367
- License
-
CC BY
BibTeX
@misc{cryptoeprint:2024/367, author = {Markku-Juhani O. Saarinen}, title = {Accelerating {SLH}-{DSA} by Two Orders of Magnitude with a Single Hash Unit}, howpublished = {Cryptology {ePrint} Archive, Paper 2024/367}, year = {2024}, doi = {10.1007/978-3-031-68376-3_9}, url = {https://eprint.iacr.org/2024/367} }