Design and Implementation of a Fast, Platform-Adaptive, AIS-20/31 Compliant PLL-Based True Random Number Generator on a Zynq 7020 SoC FPGA

Oğuz Yayla; Yunus Emre Yılmaz

Paper 2024/1442

Design and Implementation of a Fast, Platform-Adaptive, AIS-20/31 Compliant PLL-Based True Random Number Generator on a Zynq 7020 SoC FPGA

Oğuz Yayla

, Institute of Applied Mathematics, Middle East Technical University

Yunus Emre Yılmaz

, Institute of Applied Mathematics, Middle East Technical University, Aselsan Inc.

Abstract

Phase-locked loops (PLLs) integrated within field-programmable gate arrays (FPGAs) or System-on-Chip FPGAs (SoCs) represent a promising approach for generating random numbers. Their widespread deployment, isolated functionality within these devices, and robust entropy, as demonstrated in prior studies, position PLL-based true random number generators (PLL-TRNGs) as highly viable solutions for this purpose. This study explicitly examines PLL-TRNG implementations using the ZC702 Rev1.1 Evaluation Board featuring the Zynq 7020 SoC from Xilinx, utilizing a configuration involving three such boards for experimental validation. Parameters governing the PLL-TRNG are optimized using a backtracking algorithm. Additionally, a novel methodology is proposed to enhance the rate of random data bit generation while preserving entropy characteristics. Performance metrics are rigorously evaluated against the criteria set by the German Federal Office for Information Security (BSI) AIS-20/31 Tests, accompanied by detailed descriptions of the implementation process. Furthermore, the suitability of our PLL-TRNG designs, attributed to their low resource utilization, is demonstrated.

Metadata

Available format(s): PDF
Category: Implementation
Publication info: Published elsewhere. Minor revision. Springer Nature - International Joint Conferences - 17th International Conference on Computational Intelligence in Security for Information Systems (CISIS 2024)
DOI: https://doi.org/10.1007/978-3-031-75016-8_5
Keywords: random number generation PLL-TRNG AIS-20/31
Contact author(s): oguz @ metu edu tr
yeylmz @ gmail com
History: 2024-11-24: last of 3 revisions; 2024-09-16: received; See all versions
Short URL: https://ia.cr/2024/1442
License: CC BY-NC-ND

BibTeX

@misc{cryptoeprint:2024/1442,
      author = {Oğuz Yayla and Yunus Emre Yılmaz},
      title = {Design and Implementation of a Fast, Platform-Adaptive, {AIS}-20/31 Compliant {PLL}-Based True Random Number Generator on a Zynq 7020 {SoC} {FPGA}},
      howpublished = {Cryptology {ePrint} Archive, Paper 2024/1442},
      year = {2024},
      doi = {https://doi.org/10.1007/978-3-031-75016-8_5},
      url = {https://eprint.iacr.org/2024/1442}
}