Paper 2024/1019
Exploiting Clock-Slew Dependent Variability in CMOS Digital Circuits Towards Power and EM SCA Resilience
Abstract
Mathematically secured cryptographic implementations leak critical information in terms of power, EM emanations, etc. Several circuit-level countermeasures are proposed to hinder side channel leakage at the source. Circuit-level countermeasures (e.g., IVR, STELLAR, WDDL, etc) are often preferred as they are generic and have low overhead. They either dither the voltage randomly or attenuate the meaningful signature at
Note: This is under revision. It will be updated with publication details and an updated draft.
Metadata
- Available format(s)
-
PDF
- Category
- Applications
- Publication info
- Preprint.
- Keywords
- side-channel attackscorrelational power analysisTVLAgeneric countermeasureclock-based countermeasureclock-slew
- Contact author(s)
-
ghosh69 @ purdue edu
rahman88 @ purdue edu
shreyas @ purdue edu - History
- 2024-06-28: approved
- 2024-06-24: received
- See all versions
- Short URL
- https://ia.cr/2024/1019
- License
-
CC BY-NC-ND
BibTeX
@misc{cryptoeprint:2024/1019, author = {Archisman Ghosh and Md. Abdur Rahman and Debayan Das and Santosh Ghosh and Shreyas Sen}, title = {Exploiting Clock-Slew Dependent Variability in {CMOS} Digital Circuits Towards Power and {EM} {SCA} Resilience}, howpublished = {Cryptology {ePrint} Archive, Paper 2024/1019}, year = {2024}, url = {https://eprint.iacr.org/2024/1019} }