Hardware Acceleration of FHEW

Jonas Bertels; Michiel Van Beirendonck; Furkan Turan; Ingrid Verbauwhede

Paper 2023/618

Hardware Acceleration of FHEW

Jonas Bertels

, KU Leuven

Michiel Van Beirendonck

, KU Leuven

Furkan Turan

, KU Leuven

Ingrid Verbauwhede

, KU Leuven

Abstract

The magic of Fully Homomorphic Encryption (FHE) is that it allows operations on encrypted data without decryption. Unfortunately, the slow computation time limits their adoption. The slow computation time results from the vast memory requirements (64Kbits per ciphertext), a bootstrapping key of 1.3 GB, and sizeable computational overhead (10240 NTTs, each NTT requiring 5120 32-bit multiplications). We accelerate the FHEW bootstrapping in hardware on a high-end U280 FPGA. To reduce the computational complexity, we propose a fast hardware NTT architecture modified from with support for negatively wrapped convolution. The IP module includes large I/O ports to the NTT accelerator and an index bit-reversal block. The total architecture requires less than 225000 LUTs and 1280 DSPs. Assuming that a fast interface to the FHEW bootstrapping key is available, the execution speed of FHEW bootstrapping can increase by at least 7.5 times.

Metadata

Available format(s): PDF
Category: Implementation
Publication info: Published elsewhere. DDECS 2023
Keywords: FPGA Hardware Acceleration FHEW Fully Homomorphic Encryption
Contact author(s): jonas bertels @ esat kuleuven be
michiel vanbeirendonck @ esat kuleuven be
furkan turan @ esat kuleuven be
ingrid verbauwhede @ esat kuleuven be
History: 2023-05-01: approved; 2023-04-30: received; See all versions
Short URL: https://ia.cr/2023/618
License: CC BY

BibTeX

@misc{cryptoeprint:2023/618,
      author = {Jonas Bertels and Michiel Van Beirendonck and Furkan Turan and Ingrid Verbauwhede},
      title = {Hardware Acceleration of {FHEW}},
      howpublished = {Cryptology {ePrint} Archive, Paper 2023/618},
      year = {2023},
      url = {https://eprint.iacr.org/2023/618}
}