Paper 2023/610

A Needle in the Haystack: Inspecting Circuit Layout to Identify Hardware Trojans

Xingyu Meng, The University of Texas at Dallas
Abhrajit Sengupta, Qualcomm (United States)
Kanad Basu, The University of Texas at Dallas

Distributed integrated circuit (IC) supply chain has resulted in a myriad of security vulnerabilities including that of hardware Trojan (HT). An HT can perform malicious modifications on an IC design with potentially disastrous consequences, such as leaking secret information in cryptographic applications or altering operation instructions in processors. Due to the emergence of outsourced fabrication, an untrusted foundry is considered the most potent adversary in introducing an HT. This can be attributed to the asymmetric business model between the design house and the foundry; the design house is completely oblivious to the fabrication process, whereas the design IP is transparent to the foundry, thereby having full control over the layout. In order to address this issue, in this paper, we—for the first time—introduce a layout-level HT detection algorithm utilizing low-confidence classification and providing Trojan localization. We convert the IC layout to a graph and utilize Graph Neural Network (GNN)-based learning frameworks to flag any unrecognized suspicious region in the layout. The proposed framework is evaluated on AES and RS232 designs from the Trusthub benchmark suite, where it has been demonstrated to detect all nine HT-inserted designs. Finally, we open-source the full code-base for the research community at large.

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-- withdrawn --
Attacks and cryptanalysis
Publication info
Hardware Trojan DetectionIC LayoutGraph Neural NetworkConnectivity Graph
Contact author(s)
xxm150930 @ utdallas edu
as9397 @ nyu edu
kanad basu @ utdallas edu
2023-09-05: withdrawn
2023-04-28: received
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