Paper 2023/267
Proteus: A Pipelined NTT Architecture Generator
, Graz University of Technology, Graz University of Technology, Graz University of TechnologyAbstract
Number Theoretic Transform (NTT) is a fundamental building block in emerging cryptographic constructions like fully homomorphic encryption, post-quantum cryptography and zero-knowledge proof. In this work, we introduce Proteus, an open-source parametric hardware to generate pipelined architectures for the NTT. For a given parameter set including the polynomial degree and size of the coefficient modulus, Proteus can generate Radix-2 NTT architectures using Single-path Delay Feedback (SDF) and Multi-path Delay Commutator (MDC) approaches. We also present a detailed analysis of NTT implementation approaches and use several optimizations to achieve the best NTT configuration. Our evaluations demonstrate performance gain up to $1.8\times$ compared to SDF and MDC-based NTT implementations in the literature. Our SDF and MDC architectures use 1.75× and 6.5× less DSPs, and 3× and 10.5× less BRAMs, respectively, compared to state-of-the-art SDF and MDC-based NTT implementations.
Metadata
- Available format(s)
-
PDF
- Category
- Implementation
- Publication info
- Published elsewhere. Minor revision. IEEE Transactions on Very Large Scale Integration (VLSI) Systems
- DOI
- 10.1109/TVLSI.2024.3377366
- Keywords
- ParametricPipelinedNTTFHEZKP
- Contact author(s)
-
florian hirner @ iaik tugraz at
ahmet mert @ iaik tugraz at
sujoy sinharoy @ iaik tugraz at - History
- 2024-03-25: last of 3 revisions
- 2023-02-23: received
- See all versions
- Short URL
- https://ia.cr/2023/267
- License
-
CC BY
BibTeX
@misc{cryptoeprint:2023/267,
author = {Florian Hirner and Ahmet Can Mert and Sujoy Sinha Roy},
title = {Proteus: A Pipelined {NTT} Architecture Generator},
howpublished = {Cryptology {ePrint} Archive, Paper 2023/267},
year = {2023},
doi = {10.1109/TVLSI.2024.3377366},
url = {https://eprint.iacr.org/2023/267}
}
