Paper 2023/035

A Deep Analysis of two Glitch-Free Hardware Masking Schemes SESYM and LMDPL

Nicolai Müller, Ruhr University Bochum
Daniel Lammers, Ruhr University Bochum
Amir Moradi, Technische Universität Darmstadt
Abstract

In the context of masking, which is the dominant technique for protecting cryptographic hardware designs against SCA attacks, the focus has long been on the design of masking schemes that guarantee provable security in the presence of glitches. Unfortunately, achieving this comes at the cost of increased latency, since registers are required to stop glitch propagation. Previous work has attempted to reduce latency by eliminating registers, but the exponential increase in area makes such approaches impractical. Some relatively new attempts have used DRP logic styles to avoid glitches in algorithmically masked circuits. Promising approaches in this area include LMDPL and SESYM, presented at CHES 2020 and CHES 2022 respectively. Both schemes allow masking of arbitrary functions with only one cycle latency. However, even if glitches no longer occur, there are other physical defaults that may violate the security of a glitch-free masked circuit. The imbalanced delay of dual rails is a known security problem for DRP logic styles such as WDDL, but is not covered by the known security models, e.g., robust probing model. In this work, we illustrate that imbalanced signal delays pose a threat to the security of algorithmically masked circuits implemented with DRP logic, both in theory and practice. Notably, we underscore the security of LMDPL even when delays are taken into account, contrasting with the vulnerability observed in SESYM under similar conditions. Consequently, our findings highlight the critical importance of addressing imbalanced delays in the design of masked circuits using DRP logic. In particular, our findings motivate the need for an appropriate security model, and imply that relying solely on the probing security model and avoiding glitches may be insufficient to construct secure circuits.

Metadata
Available format(s)
PDF
Category
Attacks and cryptanalysis
Publication info
Published by the IACR in TCHES 2024
Keywords
Side-Channel AnalysisMaskingHardwareDRPRobust Probing ModelWDDLSESYMLMDPL
Contact author(s)
nicolai mueller @ rub de
daniel lammers @ rub de
amir moradi @ tu-darmstadt de
History
2024-03-20: last of 2 revisions
2023-01-11: received
See all versions
Short URL
https://ia.cr/2023/035
License
Creative Commons Attribution
CC BY

BibTeX

@misc{cryptoeprint:2023/035,
      author = {Nicolai Müller and Daniel Lammers and Amir Moradi},
      title = {A Deep Analysis of two Glitch-Free Hardware Masking Schemes {SESYM} and {LMDPL}},
      howpublished = {Cryptology {ePrint} Archive, Paper 2023/035},
      year = {2023},
      url = {https://eprint.iacr.org/2023/035}
}
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