ToSHI - Towards Secure Heterogeneous Integration: Security Risks, Threat Assessment, and Assurance

Nidish Vashistha; Md Latifur Rahman; Md Saad Ul Haque; Azim Uddin; Md Sami Ul Islam Sami; Amit Mazumder Shuo; Paul Calzada; Farimah Farahmandi; Navid Asadizanjani; Fahim Rahman; Mark Tehranipoor

Paper 2022/984

ToSHI - Towards Secure Heterogeneous Integration: Security Risks, Threat Assessment, and Assurance

Nidish Vashistha

, University of Florida

Md Latifur Rahman, University of Florida

Md Saad Ul Haque, University of Florida

Azim Uddin, University of Florida

Md Sami Ul Islam Sami, University of Florida

Amit Mazumder Shuo, University of Florida

Paul Calzada, University of Florida

Farimah Farahmandi

, University of Florida

Navid Asadizanjani

, University of Florida

Fahim Rahman

, University of Florida

Mark Tehranipoor, University of Florida

Abstract

The semiconductor industry is entering a new age in which device scaling and cost reduction will no longer follow the decades-long pattern. Packing more transistors on a monolithic IC at each node becomes more difficult and expensive. Companies in the semiconductor industry are increasingly seeking technological solutions to close the gap and enhance cost-performance while providing more functionality through integration. Putting all of the operations on a single chip (known as a system on a chip, or SoC) presents several issues, including increased prices and greater design complexity. Heterogeneous integration (HI), which uses advanced packaging technology to merge components that might be designed and manufactured independently using the best process technology, is an attractive alternative. However, although the industry is motivated to move towards HI, many design and security challenges must be addressed. This paper presents a three-tier security approach for secure heterogeneous integration by investigating supply chain security risks, threats, and vulnerabilities at the chiplet, interposer, and system-in-package levels. Furthermore, various possible trust validation methods and attack mitigation were proposed for every level of heterogeneous integration. Finally, we shared our vision as a roadmap toward developing security solutions for a secure heterogeneous integration.

Metadata

Available format(s): PDF
Category: Applications
Publication info: Preprint.
Keywords: Hardware Security & Assurance Secure Heterogeneous Integration Chiplets Trusted Microelectronics.
Contact author(s): nidish @ ufl edu
mdlatifur rahman @ ufl edu
haque m @ ufl edu
azim uddin @ ufl edu
md sami @ ufl edu
amazumdershuvo @ ufl edu
paul calzada @ ufl edu
farimah @ ece ufl edu
nasadi @ ece ufl edu
fahimrahman @ ece ufl edu
tehranipoor @ ece ufl edu
History: 2022-08-03: approved; 2022-08-01: received; See all versions
Short URL: https://ia.cr/2022/984
License: CC BY

BibTeX

@misc{cryptoeprint:2022/984,
      author = {Nidish Vashistha and Md Latifur Rahman and Md Saad Ul Haque and Azim Uddin and Md Sami Ul Islam Sami and Amit Mazumder Shuo and Paul Calzada and Farimah Farahmandi and Navid Asadizanjani and Fahim Rahman and Mark Tehranipoor},
      title = {{ToSHI} - Towards Secure Heterogeneous Integration: Security Risks, Threat Assessment, and Assurance},
      howpublished = {Cryptology {ePrint} Archive, Paper 2022/984},
      year = {2022},
      url = {https://eprint.iacr.org/2022/984}
}