Paper 2022/891

Secure Physical Design

Sukanta Dey, University of Florida
Jungmin Park, University of Florida
Nitin Pundir, University of Florida
Dipayan Saha, University of Florida
Amit Mazumder Shuvo, University of Florida
Dhwani Mehta, University of Florida
Navid Asadi, University of Florida
Fahim Rahman, University of Florida
Farimah Farahmandi, University of Florida
Mark Tehranipoor, University of Florida

An integrated circuit is subject to a number of attacks including information leakage, side-channel attacks, fault-injection, malicious change, reverse engineering, and piracy. Majority of these attacks take advantage of physical placement and routing of cells and interconnects. Several measures have already been proposed to deal with security issues of the high level functional design and logic synthesis. However, to ensure end-to-end trustworthy IC design flow, it is necessary to have security sign-off during physical design flow. This paper presents a secure physical design roadmap to enable end-to-end trustworthy IC design flow. The paper also discusses utilization of AI/ML to establish security at the layout level. Major research challenges in obtaining a secure physical design are also discussed.

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Publication info
CAD for Security EDA Security Physical Design Security Secure RTL to GDS-II flow Physical Layout Security Trust
Contact author(s)
sukanta dey @ ufl edu
jungminpark @ ufl edu
nitin pundir @ ufl edu
dsaha @ ufl edu
amazumdershuvo @ ufl edu
dhwanimehta @ ufl edu
nasadi @ ece ufl edu
fahimrahman @ ece ufl edu
farimah @ ece ufl edu
tehranipoor @ ece ufl edu
2022-07-08: approved
2022-07-07: received
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      author = {Sukanta Dey and Jungmin Park and Nitin Pundir and Dipayan Saha and Amit Mazumder Shuvo and Dhwani Mehta and Navid Asadi and Fahim Rahman and Farimah Farahmandi and Mark Tehranipoor},
      title = {Secure Physical Design},
      howpublished = {Cryptology ePrint Archive, Paper 2022/891},
      year = {2022},
      note = {\url{}},
      url = {}
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