Paper 2022/641
Self-Timed Masking: Implementing Masked S-Boxes Without Registers
, STMicroelectronics (France), Laboratoire Hubert Curien, Laboratoire Hubert Curien, Laboratoire Hubert Curien, French National Centre for Scientific Research, STMicroelectronics (France)Abstract
Masking is one of the most used side-channel protection techniques. However, a secure masking scheme requires additional implementation costs, e.g. random number, and transistor count. Furthermore, glitches and early evaluation can temporally weaken a masked implementation in hardware, creating a potential source of exploitable leakages. Registers are generally used to mitigate these threats, hence increasing the implementation's area and latency. In this work, we show how to design glitch-free masking without registers with the help of the dual-rail encoding and asynchronous logic. This methodology is used to implement low-latency masking with arbitrary protection order. Finally, we present a side-channel evaluation of our first and second order masked AES implementations.
Metadata
- Available format(s)
-
PDF
- Category
- Implementation
- Publication info
- Published elsewhere. CARDIS
- Keywords
- Side-channel analysis Masking Asynchronous circuits
- Contact author(s)
-
mateus simoes @ univ-st-etienne fr
lilian bossuet @ univ-st-etienne fr
vincent grosso @ univ-st-etienne fr - History
- 2022-11-25: revised
- 2022-05-24: received
- See all versions
- Short URL
- https://ia.cr/2022/641
- License
-
CC BY
BibTeX
@misc{cryptoeprint:2022/641,
author = {Mateus Simões and Lilian Bossuet and Nicolas Bruneau and Vincent Grosso and Patrick Haddad and Thomas Sarno},
title = {Self-Timed Masking: Implementing Masked S-Boxes Without Registers},
howpublished = {Cryptology {ePrint} Archive, Paper 2022/641},
year = {2022},
url = {https://eprint.iacr.org/2022/641}
}
