Paper 2022/545

Logic Locking - Connecting Theory and Practice

Elisaweta Masserova, Deepali Garg, Ken Mai, Lawrence Pileggi, Vipul Goyal, and Bryan Parno


Due to the complexity and the cost of producing integrated circuits, most hardware circuit designers outsource the manufacturing of their circuits to a third-party foundry. However, a dishonest foundry may abuse its access to the circuit's design in a variety of ways that undermine the designer's investment or potentially introduce vulnerabilities. To combat these issues, the hardware community has developed the notion of logic locking, which allows the designer to send the foundry a ``locked'' version of the original circuit. After the locked circuit has been manufactured, authorized users can unlock the original functionality with a secret key. Unfortunately, most logic locking schemes are analyzed using informal security notions, leading to a cycle of attacks and ad hoc defenses that impedes the adoption of logic locking. In this work, we propose a formal simulation-based security definition for logic locking. We then show that a construction based on universal circuits provably satisfies the definition. More importantly, we explore ways to efficiently realize our construction in actual hardware. This entails the design of alternate approaches and optimizations, and our evaluation (based on standard hardware metrics like power, area, and performance) illuminates tradeoffs between these designs.

Available format(s)
Publication info
Preprint. Minor revision.
logic lockinguniversal circuitfpga
Contact author(s)
elisawem @ andrew cmu edu
deepalig @ andrew cmu edu
2022-05-10: received
Short URL
Creative Commons Attribution


      author = {Elisaweta Masserova and Deepali Garg and Ken Mai and Lawrence Pileggi and Vipul Goyal and Bryan Parno},
      title = {Logic Locking - Connecting Theory and Practice},
      howpublished = {Cryptology ePrint Archive, Paper 2022/545},
      year = {2022},
      note = {\url{}},
      url = {}
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