Paper 2022/530
High-speed SABER Key Encapsulation Mechanism in 65nm CMOS
Malik Imran, Felipe Almeida, Andrea Basso, Sujoy Sinha Roy, and Samuel Pagliarini
Abstract
Quantum computers will break cryptographic primitives that are based on integer factorization and discrete logarithm problems. SABER is a key agreement scheme based on the Learning With Rounding problem that is quantum-safe, i.e., resistant to quantum computer attacks. This article presents a high-speed silicon implementation of SABER in a 65nm technology as an Application Specific Integrated Circuit. The chip measures 1$mm^2$ in size and can operate at a maximum frequency of 715$MHz$ at a nominal supply voltage of 1.2V. Our chip takes 10$\mu s$, 9.9$\mu s$ and 13$\mu s$ for the computation of key generation, encapsulation, and decapsulation operations of SABER. The average power consumption of the chip is 153.6$mW$. Physical measurements reveal that our design is 8.96x (for key generation), 11.80x (for encapsulation), and 11.23x (for decapsulation) faster than the best known silicon-proven SABER implementation.
Metadata
- Available format(s)
-
PDF
- Category
- Public-key cryptography
- Publication info
- Preprint. MINOR revision.
- Keywords
- ASICPost-quantumCrypto acceleratorSilicon-provenSABER
- Contact author(s)
-
malik imran @ taltech ee
felipe almeida @ taltech ee
a basso @ pgr bham ac uk
sujoy sinharoy @ iaik tugraz at
samuel pagliarini @ taltech ee - History
- 2022-05-10: received
- Short URL
- https://ia.cr/2022/530
- License
-
CC BY
BibTeX
@misc{cryptoeprint:2022/530,
author = {Malik Imran and Felipe Almeida and Andrea Basso and Sujoy Sinha Roy and Samuel Pagliarini},
title = {High-speed SABER Key Encapsulation Mechanism in 65nm CMOS},
howpublished = {Cryptology ePrint Archive, Paper 2022/530},
year = {2022},
note = {\url{https://eprint.iacr.org/2022/530}},
url = {https://eprint.iacr.org/2022/530}
}
