Paper 2022/496

Lightweight Hardware Accelerator for Post-Quantum Digital Signature CRYSTALS-Dilithium

Naina Gupta, Arpan Jati, Anupam Chattopadhyay, and Gautam Jha


The looming threat of an adversary with Quantum computing capability led to a worldwide research effort towards identifying and standardizing novel post-quantum cryptographic primitives. Post-standardization, all existing security protocols will need to support efficient implementation of these primitives. In this work, we contribute to these efforts by reporting the smallest implementation of CRYSTALS-Dilithium, a finalist candidate for post-quantum digital signature. By invoking multiple optimizations to leverage parallelism, pre-computation and memory access sharing, we obtain an implementation that could be fit into one of the smallest Zynq FPGA. On Zynq Ultrascale+, our design achieves an improvement of about 36.7%/35.4%/42.3% in Area×Time (LUTs×s) trade-off for KeyGen/Sign/Verify respectively over state-of-the-art implementation. We also evaluate our design as a co-processor on three different hardware platforms and compare the results with software implementation, thus presenting a detailed evaluation of CRYSTALS-Dilithium targeted for embedded applications. Further, on ASIC using TSMC 65nm technology, our design requires 0.227mm$^2$ area and can operate at a frequency of 1.176 GHz. As a result, it only requires 53.7μs/96.9μs/57.7μs for KeyGen/Sign/Verify operation for the best-case scenario.

Available format(s)
Publication info
post-quantumcryptographyPQCCRYSTALS-DilithiumFPGAhardwareASIChardware accelerator
Contact author(s)
naina003 @ e ntu edu sg
arpan jati @ ntu edu sg
2022-04-28: received
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Creative Commons Attribution


      author = {Naina Gupta and Arpan Jati and Anupam Chattopadhyay and Gautam Jha},
      title = {Lightweight Hardware Accelerator for Post-Quantum Digital Signature CRYSTALS-Dilithium},
      howpublished = {Cryptology ePrint Archive, Paper 2022/496},
      year = {2022},
      note = {\url{}},
      url = {}
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