Efficient ASIC Architectures for Low Latency Niederreiter Decryption

Daniel Fallnich; Shutao Zhang; Tobias Gemmeke

Paper 2022/469

Efficient ASIC Architectures for Low Latency Niederreiter Decryption

Daniel Fallnich, Shutao Zhang, and Tobias Gemmeke

Abstract

Post-quantum cryptography addresses the increasing threat that quantum computing poses to modern communication systems. Among the available "quantum-resistant" systems, the Niederreiter cryptosystem is positioned as a conservative choice with strong security guarantees. As a code-based cryptosystem, the Niederreiter system enables high performance operations and is thus ideally suited for applications such as the acceleration of server workloads. However, until now, no ASIC architecture is available for low latency computation of Niederreiter operations. Therefore, the present work targets the design, implementation and optimization of tailored archi- tectures for low latency Niederreiter decryption. Two architectures utilizing different decoding algorithms are proposed and implemented using a 22nm FDSOI CMOS technology node. One of these optimized architectures improves the decryption latency by 27% compared to a state-of-the-art reference and requires at the same time only 25% of the area.

Metadata

Available format(s): PDF
Category: Implementation
Publication info: Preprint. MINOR revision.
Keywords: Application-Specific Architecture Post-Quantum Cryptography Niederreiter Cryptosystem Hardware Implementation
Contact author(s): fallnich @ ibm com
zhang @ ids rwth-aachen de
gemmeke @ ids rwth-aachen de
History: 2022-04-22: received
Short URL: https://ia.cr/2022/469
License: CC BY

BibTeX

@misc{cryptoeprint:2022/469,
      author = {Daniel Fallnich and Shutao Zhang and Tobias Gemmeke},
      title = {Efficient {ASIC} Architectures for Low Latency Niederreiter Decryption},
      howpublished = {Cryptology {ePrint} Archive, Paper 2022/469},
      year = {2022},
      url = {https://eprint.iacr.org/2022/469}
}