Cryptology ePrint Archive: Report 2022/325

FPGA Design Deobfuscation by Iterative LUT Modification at Bitstream Level

Michail Moraitis and Elena Dubrova

Abstract: Hardware obfuscation by redundancy addition is a well-known countermeasure against reverse engineering. For FPGA designs, such a technique can be implemented with a small overhead, however, its effectiveness is heavily dependent on the stealthiness of the redundant elements. Since there are powerful tools for combinational redundancy removal, opting for sequential redundancy is believed to result in stronger obfuscation. However, in this paper, we demonstrate that it is possible to identify sequential redundancy in obfuscated SRAM FPGA designs by ensuring the full controllability of each instantiated look-up table input via iterative bitstream modification. The presented algorithm works directly on bitstream and does not require the possession of a flattened netlist. The feasibility of our approach is verified on the example of an obfuscated SNOW 3G design implemented in a Xilinx 7-series FPGA.

Category / Keywords: implementation / Obfuscation, hardware opaque predicate, SRAM FPGA, bitstream modification, reverse engineering.

Original Publication (with major differences): European Test Symposium 2022

Date: received 8 Mar 2022, last revised 19 May 2022

Contact author: micmor at kth se

Available format(s): PDF | BibTeX Citation

Version: 20220519:102638 (All versions of this report)

Short URL: ia.cr/2022/325


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