Paper 2022/1183

Fast and Efficient Hardware Implementation of HQC

Sanjay Deshpande, Yale University
Chuanqi Xu, Yale University
Mamuri Nawan, Technology Innovation Institute
Kashif Nawaz, Technology Innovation Institute
Jakub Szefer, Yale University
Abstract

This work presents a hardware design for constant-time implementation of the HQC (Hamming Quasi-Cyclic) code-based key encapsulation mechanism. HQC has been selected for the fourth-round of NIST's Post-Quantum Cryptography standardization process and this work presents first, hand-optimized design of HQC key generation, encapsulation, and decapsulation written in Verilog targeting implementation on FPGAs. The three modules further share a common SHAKE256 hash module to reduce area overhead. All the hardware modules are parametrizable at compile time so that designs for the different security levels can be easily generated. The architecture of the hardware modules includes novel, dual clock domain design, allowing the common SHAKE module to run at slower clock speed compared to the rest of the design, while other faster modules run at their optimal clock rate. The design currently outperforms the other hardware designs for HQC, and many of the fourth-round Post-Quantum Cryptography standardization process, with one of the best time-area products as well. For the combined HighSpeed design targeting lowest security level, we show that the HQC design can perform key generation in 0.1 ms, encapsulation in 0.14 ms, and decapsulation in 0.23 ms when synthesized for an Xilinx Artix 7 FPGA. As this work shows, code-based algorithms can be competitive with other schemes when optimized hardware is developed. The presented design will further be made available under open-source license.

Metadata
Available format(s)
PDF
Category
Implementation
Publication info
Preprint.
Keywords
HQC Hamming Quasi-Cyclic PQC Code-Based Cryptography Key Encapsulation Mechanism FPGA Hardware Implementation
Contact author(s)
sanjay deshpande @ yale edu
chuanqi xu @ yale edu
mamuri @ tii ae
kashif nawaz @ tii ae
jakub szefer @ yale edu
History
2022-11-02: revised
2022-09-09: received
See all versions
Short URL
https://ia.cr/2022/1183
License
Creative Commons Attribution
CC BY

BibTeX

@misc{cryptoeprint:2022/1183,
      author = {Sanjay Deshpande and Chuanqi Xu and Mamuri Nawan and Kashif Nawaz and Jakub Szefer},
      title = {Fast and Efficient Hardware Implementation of HQC},
      howpublished = {Cryptology ePrint Archive, Paper 2022/1183},
      year = {2022},
      note = {\url{https://eprint.iacr.org/2022/1183}},
      url = {https://eprint.iacr.org/2022/1183}
}
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