Paper 2022/1093

Efficient Pipelining Exploration for a High-performance CRYSTALS-Kyber Accelerator

Abstract

This work presents the fastest and the most area-time efficient design reported till date for an FPGA based hardware accelerator designed for the CRYSTALS-Kyber lattice based Key Encapsulation Mechanism (KEM) scheme. Kyber was recently chosen as the first quantum resistant KEM scheme for standardisation, after three rounds of the National Institute of Standards and Technology (NIST) PQC initiation which commenced in 2016. Kyber is based on the Module-Learning with Errors (M-LWE) class of Lattice-based cryptography, which is known to manifest efficiently on FPGAs. The design methodology revolves around aggressively enabling maximum inter-module and intra module architectural parallelisation. To facilitate maximum throughput, FIFO-based buffering is provided and balanced to act as inter/intra-module pipelining. Area-time efficiency is high by effective resource reuse in case of NTT/INTT. A single NTT/INTT is computed in 128 cycles, once the pipeline is full. The FPGA based implementation results show that compared to the state-of-the-art, the proposed architecture delivers 24-52% speedups at three different security levels on Artix-7 and Zynq UltraScale+ devices, 50-75% reduction in DSPs and no BRAM resources usage for comparable security levels. Consequently, the AT product efficiency is reported to be 48-54% higher in comparison with the state-of-the-art designs.