Cryptology ePrint Archive: Report 2021/749

Three Halves Make a Whole? Beating the Half-Gates Lower Bound for Garbled Circuits

Mike Rosulek and Lawrence Roy

Abstract: We describe a garbling scheme for boolean circuits, in which XOR gates are free and AND gates require communication of $1.5\kappa + 5$ bits. This improves over the state-of-the-art "half-gates" scheme of Zahur, Rosulek, and Evans (Eurocrypt 2015), in which XOR gates are free and AND gates cost $2\kappa$ bits. The half-gates paper proved a lower bound of $2\kappa$ bits per AND gate, in a model that captured all known garbling techniques at the time. We bypass this lower bound with a novel technique that we call slicing and dicing, which involves slicing wire labels in half and operating separately on those halves. Ours is the first to bypass the lower bound while being fully compatible with free-XOR, making it a drop-in replacement for half-gates. Our construction is proven secure from a similar assumption to prior free-XOR garbling (circular correlation-robust hash), and uses only slightly more computation than half-gates.

Category / Keywords: cryptographic protocols / garbled circuits

Original Publication (with minor differences): IACR-CRYPTO-2021

Date: received 3 Jun 2021

Contact author: rosulekm at oregonstate edu, ldr709@gmail com

Available format(s): PDF | BibTeX Citation

Version: 20210607:062827 (All versions of this report)

Short URL: ia.cr/2021/749


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