Cryptology ePrint Archive: Report 2021/536

Analyzing the Potential of Transport Triggered Architecture for Lattice-based Cryptography Algorithms

Latif AKÇAY and Berna ÖRS

Abstract: Lattice-based structures offer considerable possibilities for post-quantum cryptography. Recently, many algorithms have been built on hard lattice problems. The three of the remaining four in the final round of the post-quantum cryptography standardization process use lattice-based methods. Especially in embedded systems, these algorithms should be operated effectively. In this study, the potential of transport triggered architecture is examined in this sense. We try to compare open source RISC-V processors with our transport triggered architecture processors under fair conditions. Thus, we aim to provide a base architecture for developing application specific processors for post-quantum cryptography, which is becoming an increasingly urgent research area. The tests performed are implemented on the same FPGA and evaluated as performance, resource utilization, average power and total energy consumption. Regardless of the algorithm, our design exhibit better results than RISC-V processors for all tests. It seems to be 2x - 3x faster, 2x - 2.5x smaller and consumes 2.5x - 5x less energy than RISC-V competitors. We also share how the results vary for many different configurations of our processor that can be easily converted. The obtained findings show that the transport triggered architecture is a promising option on developing application-specific processors for lattice-based post-quantum cryptography applications.

Category / Keywords: implementation / TTA, RISC-V, lattice-based cryptography, post-quantum cryptography, processor architecture, application specific processor, Kyber, NewHope, Saber, NTRU

Date: received 22 Apr 2021

Contact author: lakcay at bayburt edu tr

Available format(s): PDF | BibTeX Citation

Version: 20210423:123347 (All versions of this report)

Short URL: ia.cr/2021/536


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