Cryptology ePrint Archive: Report 2021/485

A Hardware Accelerator for Polynomial Multiplication Operation of CRYSTALS-KYBER PQC Scheme

Ferhat Yaman and Ahmet Can Mert and Erdinç Öztürk and Erkay Savaş

Abstract: Polynomial multiplication is one of the most time-consuming operations utilized in lattice-based post-quantum cryptography (PQC) schemes. CRYSTALS-KYBER is a lattice-based key encapsulation mechanism (KEM) and it was recently announced as one of the four finalists at round three in NIST's PQC Standardization. Therefore, efficient implementations of polynomial multiplication operation are crucial for high-performance CRYSTALS-KYBER applications. In this paper, we propose three different hardware architectures (lightweight, balanced, high-performance) that implement the NTT, Inverse NTT (INTT) and polynomial multiplication operations for the CRYSTALS-KYBER scheme. The proposed architectures include a unified butterfly structure for optimizing polynomial multiplication and can be utilized for accelerating the key generation, encryption and decryption operations of CRYSTALS-KYBER. Our high-performance hardware with 16 butterfly units shows up to 112×, 132× and 109× improved performance for NTT, INTT and polynomial multiplication, respectively, compared to the high-speed software implementations on Cortex-M4.

Category / Keywords: cryptographic protocols / CRYSTALS-KYBER, PQC, NTT, Polynomial Multiplication, Hardware

Original Publication (in the same form): 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE)

Date: received 15 Apr 2021

Contact author: ferhatyaman at sabanciuniv edu,ahmetcanmert@sabanciuniv edu,erdinco@sabanciuniv edu,erkays@sabanciuniv edu

Available format(s): PDF | BibTeX Citation

Version: 20210416:111615 (All versions of this report)

Short URL: ia.cr/2021/485


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