Cryptology ePrint Archive: Report 2021/309

SoCCAR: Detecting System-on-Chip Security Violations Under Asynchronous Resets

Xingyu Meng and Kshitij Raj and Atul Prasad Deb Nath and Kanad Basu and Sandip Ray

Abstract: Modern SoC designs include several reset domains that enable asynchronous partial resets while obviating complete system boot. Unfortunately, asynchronous resets can introduce security vulnerabilities that are difficult to detect through traditional validation. In this paper, we address this problem through a new security validation framework, SoCCCAR, that accounts for asynchronous resets. The framework involves (1) efficient extraction of reset-controlled events while avoiding combinatorial explosion, and (2) concolic testing for systematic exploration of the extracted design space. Our experiments demonstrate that SoCCAR can achieve almost perfect detection accuracy and verification time of a few seconds on realistic SoC designs.

Category / Keywords: applications / Hardware Security Verification, SoC, Concolic Testing

Original Publication (with minor differences): Design Automation Conference

Date: received 8 Mar 2021

Contact author: kanad basu at utdallas edu

Available format(s): PDF | BibTeX Citation

Version: 20210309:135021 (All versions of this report)

Short URL: ia.cr/2021/309


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