Paper 2021/1444

Streamlined NTRU Prime on FPGA

Bo-Yuan Peng, Adrian Marotzke, Ming-Han Tsai, Bo-Yin Yang, and Ho-Lin Chen

Abstract

We present a novel full hardware implementation of Streamlined NTRU Prime, with two variants: A high-speed, high-area implementation, and a slower, low-area implementation. We introduce several new techniques that improve performance, including a batch inversion for key generation, a high-speed schoolbook polynomial multiplier, an NTT polynomial multiplier combined with a CRT map, a new DSP-free modular reduction method, a high-speed radix sorting module, and new en- and decoders. With the high-speed design, we achieve the to-date fastest speeds for Streamlined NTRU Prime, with speeds of 5007, 10989 and 64026 cycles for encapsulation, decapsulation, and key generation respectively, while running at 285 MHz on a Xilinx Zynq Ultrascale+. The entire design uses 40060 LUT, 26384 flip-flops, 36.5 Bram and 31 DSP.

Metadata
Available format(s)
PDF
Category
Implementation
Publication info
Preprint. MINOR revision.
Keywords
NTRU PrimeHardware ImplementationLattice CryptographyPost-Quantum CryptographyFPGA
Contact author(s)
adrian marotzke @ tuhh de
bypeng @ crypto tw
by @ crypto tw
History
2022-04-09: revised
2021-10-27: received
See all versions
Short URL
https://ia.cr/2021/1444
License
Creative Commons Attribution
CC BY

BibTeX

@misc{cryptoeprint:2021/1444,
      author = {Bo-Yuan Peng and Adrian Marotzke and Ming-Han Tsai and Bo-Yin Yang and Ho-Lin Chen},
      title = {Streamlined NTRU Prime on FPGA},
      howpublished = {Cryptology ePrint Archive, Paper 2021/1444},
      year = {2021},
      note = {\url{https://eprint.iacr.org/2021/1444}},
      url = {https://eprint.iacr.org/2021/1444}
}
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