Cryptology ePrint Archive: Report 2021/1444

Streamlined NTRU Prime on FPGA

Bo-Yuan Peng and Adrian Marotzke and Ming-Han Tsai and Bo-Yin Yang and Ho-Lin Chen

Abstract: We present a novel full hardware implementation of Streamlined NTRU Prime, with two variants: A high-speed, high-area implementation, and a slower, low-area implementation. We introduce several new techniques that improve performance, including a batch inversion for key generation, a high-speed schoolbook polynomial multiplier, an NTT polynomial multiplier combined with a CRT map, a new DSP-free modular reduction method, a high-speed radix sorting module, and new en- and decoders. With the high-speed design, we achieve the to-date fastest speeds for Streamlined NTRU Prime, with speeds of 5007, 10989 and 64026 cycles for encapsulation, decapsulation, and key generation respectively, while running at 285 MHz on a Xilinx Zynq Ultrascale+. The entire design uses 40060 LUT, 26384 flip-flops, 36.5 Bram and 31 DSP.

Category / Keywords: implementation / NTRU Prime, Hardware Implementation, Lattice Cryptography, Post-Quantum Cryptography, FPGA

Date: received 27 Oct 2021

Contact author: adrian marotzke at tuhh de, bypeng at crypto tw, by at crypto tw

Available format(s): PDF | BibTeX Citation

Version: 20211027:193557 (All versions of this report)

Short URL: ia.cr/2021/1444


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