Paper 2021/1444
Streamlined NTRU Prime on FPGA
, National Taiwan University, Academia Sinica, Hamburg University of Technology, NXP (Germany), Academia SinicaAbstract
We present a novel full hardware implementation of Streamlined NTRU Prime, with two variants: A high-speed, high-area implementation, and a slower, low-area implementation. We introduce several new techniques that improve performance, including a batch inversion for key generation, a high-speed schoolbook polynomial multiplier, an NTT polynomial multiplier combined with a CRT map, a new DSP-free modular reduction method, a high-speed radix sorting module, and new en- and decoders. With the high-speed design, we achieve the to-date fastest speeds for Streamlined NTRU Prime, with speeds of 5007, 10989 and 64026 cycles for encapsulation, decapsulation, and key generation respectively, while running at 285 MHz on a Xilinx Zynq Ultrascale+. The entire design uses 40060 LUT, 26384 flip-flops, 36.5 Bram and 31 DSP.
Metadata
- Available format(s)
-
PDF
- Category
- Implementation
- Publication info
- Published elsewhere. Journal of Cryptographic Engineering
- DOI
- 10.1007/s13389-022-00303-z
- Keywords
- NTRU Prime Hardware Implementation Lattice Cryptography Post-Quantum Cryptography FPGA
- Contact author(s)
-
bypeng @ crypto tw
adrian marotzke @ tuhh de
r08943151 @ ntu edu tw
by @ crypto tw
holinchen @ ntu edu tw - History
- 2022-11-18: last of 3 revisions
- 2021-10-27: received
- See all versions
- Short URL
- https://ia.cr/2021/1444
- License
-
CC BY
BibTeX
@misc{cryptoeprint:2021/1444,
author = {Bo-Yuan Peng and Adrian Marotzke and Ming-Han Tsai and Bo-Yin Yang and Ho-Lin Chen},
title = {Streamlined NTRU Prime on FPGA},
howpublished = {Cryptology ePrint Archive, Paper 2021/1444},
year = {2021},
doi = {10.1007/s13389-022-00303-z},
note = {\url{https://eprint.iacr.org/2021/1444}},
url = {https://eprint.iacr.org/2021/1444}
}
