Cryptology ePrint Archive: Report 2021/1212

SPEEDY on Cortex--M3: Efficient Software Implementation of SPEEDY on ARM Cortex--M3

Hyunjun Kim and Kyungbae Jang and Gyeongju Song and Minjoo Sim and Siwoo Eum and Hyunji Kim and Hyeokdong Kwon and Wai-Kong Lee and Hwajeong Seo

Abstract: The SPEEDY block cipher suite announced at CHES 2021 shows excellent hardware performance. However, SPEEDY was not designed to be efficient in software implementations. SPEEDY's 6-bit sbox and bit permutation operations generally do not work efficiently in software. We implemented SPEEDY block cipher by applying the implementation technique of bit slicing. As an implementation technique of bit slicing, SPEEDY can be operated in software very efficiently and can be applied in microcontroller. By calculating the round key in advance, the performance on ARM Cortex-M3 for SPEEDY-5-192, SPEEDY-6-192, and SPEEDY-7-192 are 65.7, 75.25, and 85.16 clock cycles per byte (i.e. cpb), respectively. It showed better performance than AES-128 constant-time implementation and GIFT constant-time implementation in the same platform. Through this, we conclude that SPEEDY can show good performance on embedded environments.

Category / Keywords: implementation / Software Implementation , SPEEDY, ARM Cortex--M3

Date: received 16 Sep 2021

Contact author: thdrudwn98 at gmail com, starj1023 at gmail com, khj930704 at gmail com, shuraatum at gmail com, minjoos9797 at gmail com, khj1594012 at gmail com, hwajeong84 at gmail com, waikonglee at gachon ac kr, korlethean at gmail com

Available format(s): PDF | BibTeX Citation

Version: 20210917:092503 (All versions of this report)

Short URL: ia.cr/2021/1212


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