Cryptology ePrint Archive: Report 2021/1202

Design Space Exploration of SABER in 65nm ASIC

Malik Imran and Felipe Almeida and Jaan Raik and Andrea Basso and Sujoy Sinha Roy and Samuel Pagliarini

Abstract: This paper presents a design space exploration for SABER, one of the finalists in NIST’s quantum-resistant public-key cryptographic standardization effort. Our design space exploration targets a 65nmASIC platform and has resulted in the evaluation of 6 different architectures. Our exploration is initiated by setting a baseline architecture which is ported from FPGA. In order to improve the clock frequency (the primary goal in our exploration), we have employed several optimizations: (i) use of compiled memories in a ‘smart synthesis’ fashion, (ii) pipelining, and (iii) logic sharing between SABER building blocks. The most optimized architecture utilizes four register files, achieves a remarkable clock frequency of 1𝐺𝐻𝑧 while only requiring an area of 0.314𝑚𝑚2. Moreover, physical synthesis is carried out for this architecture and a tapeout-ready layout is presented. The estimated dynamic power consumption of the high-frequency architecture is approximately 184mW for key generation and 187mW for encapsulation or decapsulation operations. These results strongly suggest that our optimized accelerator architecture is well suited for high-speed cryptographic applications.

Category / Keywords: public-key cryptography / Application specific integrated circuits, Hardware security implementation, Cryptography

Date: received 16 Sep 2021

Contact author: malik imran at taltech ee, felipe almeida at taltech ee, jaan raik at taltech ee, a basso at pgr bham ac uk, sujoy sinharoy at iaik tugraz at, samuel pagliarini at taltech ee

Available format(s): PDF | BibTeX Citation

Version: 20210917:092107 (All versions of this report)

Short URL: ia.cr/2021/1202


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